module instFetch (
    input   logic           clk,
    input   logic           rst_n,

    output  logic   [7:0]   IMem_Addr,
    input   logic   [31:0]  IMem_Data,
    output  logic   [31:0]  Inst_code,

    output  logic   [31:0]  PC_new,

    input   logic   [1:0]   PC_s,
    input   logic   [31:0]  rs_Data,
    input   logic   [31:0]  offset,
    input   logic   [25:0]  address
);


logic [31:0] pc;

always_ff @( negedge clk, negedge rst_n ) begin
    if(!rst_n) begin
        pc <= 'd0;
    end
    else begin
        case (PC_s)
            2'd0: pc <= PC_new;
            2'd1: pc <= rs_Data;
            2'd2: pc <= PC_new + (offset << 2);
            2'd3: pc <= {PC_new[31:28], address, 2'b0};
        endcase
    end
end

always_comb begin
    IMem_Addr   = pc[7:0];
    Inst_code   = IMem_Data;
    PC_new      = pc + 'd4;
end


endmodule
